It is the size of a fingernail.
And inside that tiny sliver of silicon, there are almost 100 billion transisters. Not a billion. Not ten billion. Nearly double the density of any previous state-of-the-art chip. IBM calls this their 0.7 nanometre prototype, though calling it “0.7 nm” is already a bit of a lie, a marketing shorthand for something much weirder than just small.
The old rules don’t apply anymore.
For sixty years, the industry chased smaller. Shrink the transistor. 10 nanometers, then 5, then 2. Smaller meant denser, faster, cheaper power. Simple logic. But we hit a wall. A physics wall. Huiming Bu, a researcher at IBM, puts it bluntly: those size names? They’re decoupled from reality now. “0.7 nm” isn’t a physical measurement. It’s a label. A brand.
The actual breakthrough isn’t shrinking horizontally. It’s building vertically.
“Our whole industry has been scaling… in the X and Y axis for all 60-plus years. It’s the first time we’ll enable scaling in the Z direction.”
Imagine two layers of working 2-nm chips (the kind Apple is already eyeing for the next iPhone) stacked on top of each other. Sounds simple, right? Try connecting billions of wires between those layers without melting the silicon or creating a heat sink that boils water. IBM claims they did it. They developed a way to bond two layers that handles the electrical connections, stays cool, and can actually be mass-produced. Fifteen years of development for one process.
Why does anyone care?
Because Moore’s Law is dying on the vine, or at least bleeding heavily. You can’t just squeeze more juice out of flat silicon. You have to stack it.
IBM promises this 10×15 millimetre wonder will be 50% more performant and 70% more energy efficient than today’s leaders. Commercial devices? Maybe. In ten years, they hope. Ten years is an eternity in tech, longer than some of us have been paying rent.
The roadmap is set by IMEC, the Belgian research outfit that acts like the UN for chipmakers. IBM’s stack fits their timeline. Others will follow, likely. It’s too expensive for any one company to gamble on the future alone.
But it’s messy. Really messy.
Owen Guy, a physicist at Swansea University, thinks the whole field is becoming a circus. Other manufacturers claim similar densities, but they’re cheating—using thick substrates to separate layers, making true 3D connectivity impossible. Hard to cool, hard to connect. Smoke and mirrors.
We are pushing against the laws of physics now.
Some parts of IBM’s new chips are fifteen atoms thick. That is tiny. Current leakage, quantum weirdness, thermal explosions waiting to happen. Guy points out that shrinking transistors doesn’t make your laptop smaller anymore. It makes it last longer on battery. It saves power in data centers. That’s the game now. Efficiency, not portability.
Then there is the manufacturing nightmare.
Chips are carved from 300-millimeter wafers, containing trillions of transistors, cut into batches. Adding IBM’s untested Z-axis stack to this ballet of precision is… daunting. The machinery performs thousands of operations, laying down insulation and chemicals measured in atoms. Break the flow, break the global supply chain.
Is it worth the headache?
IBM says yes. The rest of the world will find out soon enough. Or maybe not. Some dream of 0.2-nanometer chips. One atom wide. One electron controlling the circuit. That is the ultimate limit. We won’t reach it until 2050, probably, and by then, classical silicon will have surrendered entirely to quantum mechanics.
Until then, we stack.
